Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes a non-volatile memory made up of floating-gate memory cells called flash memory. Computer applications use flash memory to store BIOS firmware. Peripheral devices such as printers store fonts and forms on flash memory. Digital cellular and wireless applications consume large quantities of flash memory and are continually pushing for lower voltages and power demands. Portable applications such as digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment also use flash memory as a medium to store data.
Memory devices are usually tested as part of the manufacturing process, and may also be tested by original equipment manufacturers (OEMs) making use of the memory devices, to help insure their reliability. These tests are generally performed by dedicated testing equipment, or tester hardware, capable of testing and communicating with multiple memory devices to increase the number of devices that can be tested in a given period of time.
During testing, many aspects of memory device operation may be performed. Some aspects of operation may be tested in a manner that is inconsistent with typical device operation. One example is the ability of the memory device to perform erase operations on its memory cells. While such erase operations may be performed on only one block of memory cells during normal use of the device, the erase operation in testing may be performed on many more cells simultaneously, such as multiple blocks of memory cells. Erase operations during testing may even extend to simultaneously erasing the entire memory array.
The erase operation is often performed in this manner, i.e., many blocks in parallel, to reduce the amount of time required of the tester hardware. If the tests were not performed in this manner, the tester hardware would need to individually address each block of memory cells and initiate an erase operation. This would increase the demands on the processor of the tester hardware. By increasing the number of memory cells to be erased in one erase operation on a memory device, the tester hardware can more quickly move on to the next memory device, thereby reducing the amount of processor time necessary for testing each device. This permits the tester hardware to test more memory devices concurrently. However, it is noted that erasing large numbers of memory cells may require power levels that are beyond the capabilities of the on-chip charge pumps used to generate the erase potentials, thus necessitating the use of externally-supplied erase potentials.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative methods and apparatus to aid in erasing portions of a flash memory device during testing.